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19.4.5.1.2 Toshiba s Technology Map. The packaging technology map is a simple technique to predict a PWB, Chip-On-Board, or MCM-L wiring demand and its assembly complexity. By plotting components per square inch (or components per square centimeter) against average leads per component on a Log-log graph (see Fig. 19.11), you can calculate the wiring demand WD in inches per square inch (or centimeters per square centimeters) and assembly complexity in leads per square inch (or leads per square centimeter). Eqs. 19.7 and 19.8 show the equations for these two metrics. Wiring Demand WD = b (comp)0.5 (leads) where b = wiring coefficient (typically 3.5 but can vary from 2.5 4.0 on average; notes/net is a good approximation) comp = components per board area in sq. in. or sq. cm. leads = average leads (connections) per component Assembly Complexity = (comp) (leads) comp = components per board area in sq. in. or sq. cm. leads = average leads (connections) per component (19.8) (19.7)

public void buttonPressBinding(ActionEvent actionEvent) { // Add event code here... AttributeBinding attr = (AttributeBinding)getBindings().getControlBinding("CustLastName"); String selectedCust = (String)attr.getInputValue(); attr.setInputValue(selectedCust.toLowerCase()); }

50 70 100 200 300 60 80 120 160 180 240 320

Using these two equations, Fig. 19.12 shows lines of constant wiring demand (in cm. per sq. cm or in. per sq. in.) and assembly complexity (in leads per sq. cm. or sq. in.) that can be plotted on this chart (see Fig. 19.11). 19.4.5.1.3 HP s Design Density Index. Another metric is called the Design Density Index (DDI). It is a correlation of the actual design rules for a PWB compared to the DDI metric. Equation 19.9 gives DDI, and Fig. 19.13 shows a typical calibration chart. DDI = 13.6 (EIC/board area)^1.53 where EIC (equivalent integrated circuits) = total component leads/16 board area = top surface area of a PCB (sq. inch.) (19.9)

program 21-13

The chart shown in Fig. 9.13 gives a good visual record in PWB layout of a company s efficiency. As various PC boards are charted, their DDIs form a distribution. This distribution is a form of layout efficiency (e) since at the bottom of the distribution, more EICs are connected than at the top of the distribution. 19.4.5.1.4 Density of Equivalent ICs. EIC per unit area has been a traditional measure of density since the introduction of CAD systems in the early 1970s. A simple measure of the number of electrical connections required per unit area of the board, it remains in use with

surface mounting technology and is usually referred to as EIC density. An EIC is the total number of leads of the components divided by 14 or 16, the old number of pins on a dualinline package (DIP). Many people also use 20 as a divisor. Equation 19.10 defines EIC density mathematically in EIC/sq. in. EIC Density = Connections/16/Board Area where Connections = total component leads Board Area = top surface board area (in sq. cm. or sq. in.) (19.10)

DDI = 13.6 x [EIC/sq. in.)^1.53]

Typical Example of Wiring Demand Calculation As an example, take a typical consumer electronic board with these characteristics:

Design: consumer PCB, all through hole components Components: 86

Listing for Program LCDRoutines4 (continued)

Leads: 1,540 Size: 19.6 in. 19.5 in. = 57 sq. in. EIC/sq. in. = 110/57 sq. in. = 1.93 (using Eq. 19.10) DDI = 13.6 ( 1.93 ) 1.53 = 319.7 ~ Figure19.13 advises two tracks on two signal layers (using Eq. 19.9).

NOTe This example assumes you have written the previously described getBindings() method. Note also that the value passed to getControlBinding() must exactly match the name of the binding or you will get an exception. In the preceding code, an object, AttributeBinding, is used to reference an attribute binding to CustLastName. A call to getInputValue() and setInputValue() can be used to read and write the values referenced by the attribute binding.

The metrics for PWB and chip-on-board (COB) fabrication involve with trade-offs between the performance objectives and the PWB price. Calculating prices requires the PCB characteristics and manufacturing yield. Manufacturing yield requires producibility estimates. Three items are required to predict PCB prices:

Fabrication complexity matrix Prediction of producibility and first-pass yield Relative price as a function of a price index

Fabrication Complexity Matrix The fabrication complexity matrix is supplied by a PWB fabricator. It relates the various design choices on a PWB to design points. These points are based on the actual prices that a fabricator will charge for these features. They are calculated by dividing the actual costs and the values by the smallest nonzero amount. Typical factors that fabricators can use to price a printed wiring board include the following:

Size of the board and number that fit on a panel Number of layers Material of construction Trace and space widths Total number of holes Smallest hole diameter Solder mask and component legends Final metalization or finish Gold-plated edge connectors Factors specific to the design

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A typical fabrication complexity matrix would look like Table 19.3. This is not a complete matrix, but does show the design factors and the design points assigned to each. 19.5.2 Predicting Producibility The simple truth about printed circuit boards, multichip modules, and hybrid circuits is that the design factors such as those listed previously can have a cumulative effect on manufacturing yield. These factors all affect producibility. Specifications can be selected that individually may not adversely affect yields but cumulatively can significantly reduce yields. A simple